About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

The Central Engineering - AMS Signal Integrity Signal Integrity Team is responsible for establishing and maintaining interconnect Signal Integrity (SI) and Power Integrity (PI) design rules for Marvell COMPHY, D2D, DDR and other analog misc. IP. This includes overseeing floorplan, Redistribution Layer (RDL) design, bump pattern, interposer and package routing, and PCB layout design rule to ensure optimal system performance.

What You Can Expect

Collaborating with cross-functional teams: Work closely with circuit design, applications engineering, packaging technology, and board design teams to define and implement system interconnects that meet both internal specifications and customer requirements.Conducting simulations and analysis: Perform SI/PI simulations and analysis to predict and mitigate potential issues in the design phase.Developing SI/PI design rules: Create and maintain design rules for floorplan, RDL, bump patterns, 2.5D/2D package, and PCB layouts to ensure signal and power integrity across the system.SI/PI model release: Release Die models including IBIS-AMI, power current profiles and on-die decoupling caps to internal BU and external customer.Providing technical support: Offer technical support and guidance to other teams and customers regarding SI/PI issues and best practices.

What We're Looking For

Bachelor’s degree in electrical engineering and 8+ years of related professional experience or Master’s degree/PhD in electrical engineering with 5+ years of experience.Solid transmission line and EM background is a must.Must have good knowledge about interposer/package/PCB design rules, routing feasibility and SI/PI design consideration.Experiences in die-to-die interposer, package and PCB high density trial routing study by using Cadence tool such as APD or PCB editor is  good plus.System-level SI/PI simulation experience such as DDR/NAND and PCIe/Ethernet is preferred.Always do the right thing and represent Marvell with ethics and integrity.

Expected Base Pay Range (USD)

137,510 - 206,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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