About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a core member of Marvell's Central Physical Design team, you’ll provide backend design services to Marvell's SoC groups, working across a variety of complex designs that underpin data center, server, and networking applications. This team is dedicated to achieving high-performance and low-power goals for Marvell’s optical DSP and networking solutions, supporting multiple business models and targeted at the forefront of data infrastructure.

What You Can Expect

As a Principal Physical Design Engineer specializing in chip-level Place and Route (PNR), you will play a pivotal role in defining Marvell’s physical design process and flow, ensuring successful delivery of high-performance designs in advanced technology nodes. Leveraging your expertise, you’ll directly influence the quality of Marvell’s next-generation products, guiding backend implementation from concept to tapeout and providing technical leadership on challenging SoC projects.

Hands-On Chip-Level Physical Design:Lead chip-level PNR activities, from floor planning and power grid design to clock tree synthesis, routing, and timing closure.Perform detailed timing, power and signal integrity signoff, including IR drop and crosstalk analysis, ensuring designs meet stringent performance and reliability targets.Manage physical verification tasks (DRC, LVS, antenna) to meet process and quality standards required for advanced semiconductor nodes.Leadership and Collaboration:Act as a technical leader, guiding a team of physical design engineers on project-level backend implementation, and coordinate with frontend, integration, and verification teams.Develop and refine physical design methodologies and flows, collaborating cross-functionally to optimize design efficiency and alignment with project goals.Mentor and develop junior engineers, fostering an environment that encourages innovation and excellence.Process and Tool Optimization:Use scripting skills to streamline and automate workflows (Makefile, Tcl, Perl), enhancing design efficiency across projects.Maintain a deep understanding of physical design tools, including Cadence Innovus, Synopsys IC Compiler, and Fusion Compiler, ensuring best practices in tool use and integration.

At Marvell, you’ll have the opportunity to work on industry-leading designs, pushing the boundaries of what’s possible in the semiconductor field. This Principal Physical Design Engineer role offers an impactful platform to shape Marvell’s next generation of products and lead a team committed to excellence and innovation.

What We're Looking For

Education & Experience:Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.10+ years of hands-on experience in physical design and verification, with proven success in chip-level PNR and tape-outs of complex SoC designs.Technical Expertise:Demonstrated ability to lead chip-level backend implementation and deliver on schedule.Familiar with hierarchical design strategies and deep sub-micron technology (e.g., N7/N5), with knowledge of current design technologies used in major foundries.Extensive experience with timing analysis (Tempus, PrimeTime) and EM/IR-Drop/crosstalk analysis tools (Voltus, Celtic, PTSI, AstroRail).Skilled in physical verification tools and logic equivalence tools (LEC, Formality, Calibre) and extraction tools (QRC, StarRC).Programming & Automation Skills:Advanced scripting abilities, especially in Makefile, Tcl, and Perl, with a focus on improving backend process efficiency.Key Attributes:Detail-oriented, self-motivated, and an effective communicator, with a collaborative team-oriented approach.Planning, and resourcing physical design work, cross functional collaboration.

Expected Base Pay Range (USD)

137,510 - 206,000, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

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