The Microsoft Silicon Engineering Team is seeking a **Principal Front -End Silicon CAD Manager** to join our Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and quality assurance checks across Front-End areas such as Continuous Integration, Source Control Management, Verilog Design, Design Verification, Validation, Emulation and IP integration. This team supports numerous simultaneous projects within Microsoft by developing workflows and software for our design engineers so that they can deliver cutting-edge silicon solutions for Microsoft. Relocation assistance is available for this role within the US. **Responsibilities** In this role, you will have a board scope and will lead and manage a team of engineers that will: + Be part of a central Front-End CAD (Computer Aided Design) team that drives common Front-End (FE) methodologies for SoC and IP design. + Be an expert in the FE domain and act in partnership with the execution team. + Provide leadership to the design community for the FE CAD domain. + Work with stakeholders across the Microsoft Silicon group to collect TFM requirements. + Develop, enhance, and integrate common design and verification IP for organization-wide use.  + Work with EDA vendors to adopt the most optimal solutions for silicon verification and design. + Embody our Culture (https://www.microsoft.com/en-us/about/corporate-values) and Values (https://careers.microsoft.com/us/en/culture) **Qualifications** **Required Qualifications: ** ** ** + 9+ years of related technical engineering experience + OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experience + OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience + OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience. + 9+ years of experience in digital design and CAD tool development. + 5+ years of experience in personnel management. + Familiar with most Front-End Tools, Flows and Methodologies: Logic design, Design Verification, Design for Test (DFT), FE Handoff to Physical Design, Validation, Emulation and FPGA design, Static Tool Analysis, Synthesis, Design Integration, Design and Verification IP Libraries, Verilog Generators, and Low Power design. **Other Requirements:** Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. **Additional Preferred: ** + MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. + Experience using industry standard HDLs like SystemVerilog.  + Experienced writing scripts/software with industry standard languages such as Python, TCL, Perl, C/C++ or SystemC. + 15+ years of relevant experience in FE CAD; 7+ years in personnel management. + Experience with CI/CD, and integration into SCM systems. + Expertise in Computer Architecture, as well as CPU/SoC design principles. + **Management of Software CAD Teams:** + In-depth knowledge in scripting/software development with industry standard languages such as Python, TCL, C/C++ or SystemC. + Experience architecting software solutions for silicon design solutions. + **Management of** **Logic Design CAD** **Teams:** + In-depth knowledge of Front-End workflows, methodologies, and best practices. Ability to design and verify reusable design components. + Direct experience with Front-End to Physical Design hand-off (RTL to PD) + **Managing** **Verification, Emulation, Virtual IP** **CAD teams** **:** + In-depth knowledge of verification workflows, methodologies, and best practices.  + Experience with the debug and bring-up of SOC and sub-system level designs.  + Experience defining, developing, and using verification environments in industry standard languages like System Verilogand UVM. + Experience with VIP development or integrating and using 3rd party VIPs.  + Knowledge or experience with Formal verification and/or Emulation.  + Experience with FPGA-based Prototyping systems.  Silicon Engineering M5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay Microsoft will accept applications for the role until November 8, 2024. Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .