At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality. The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control. The candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies. This includes but is not limited to: + Digital architecture that has an understanding of the trade-offs for power, performance, and area + Drive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process + Understanding of synthesis, constraint generation, power management and DFT + Understanding of low-power designs and features (power islands, state retention, isolation) + Work with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation + Familiarity with uC Based subsystems and their architecture Qualifications + 7+ Years’ experience in working with Digital Design and Architecture. + Must have good written and verbal cross-functional communication skills. + Proven experience in most of the following: + Design Architecture + Design implementation + Embedded uC Designs + Synthesis and SDC Creation + Scripting of design automation + Debugging verification test cases / SVA’s to cover the design + Knowledge of existing Serial standards such as PCIE, USB, Ethernet, etc. + Must be comfortable interacting across the IPG development team including the ability to work with Mixed-signal, Verification and Analog teams + Knowledge of multiple programming languages. System Verilog, Python, C/C++, etc, are a plus + Working knowledge of revision control tools such as Perforce, Git, SVN is a plus + Education Level : Bachelor's Degree (MSEE Preferred) We’re doing work that matters. Help us solve what others can’t. Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. 
 Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.