Company:Qualcomm Atheros, Inc.

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast paced Integrated Wireless

Technology team you will be working on low power next generation Wifi subsystem related Physical design implementation. You will also be actively involved in Floor Planning (FP), Place and Route (P&R) , Physical Verification(PV), Power/Performance/Area (PPA) optimization and closure of blocks with high QOR.

Responsibilities:

The candidate will be responsible to complete critical block level physical design implementation from netlist to GDS, debug issues and proactively find solutions.  This candidate will be working with Design, Synthesis and STA teams closely to provide physical design feedback and improve the overall block’s physical design PPA and QOR. This candidate will also be actively involved in Floor Planning (FP), Placement, Clock Tree Synthesis (CTS), STA closure, and Physical verification closure for critical WiFi blocks. The candidate will also work on the automation of PD flows to accommodate fast paced changes coming from the logic design team and will be involved in all critical decisions for Block level Physical Implementation.

Experience in low power physical design with ICC2/FC tool set, good debugging and scripting (TCL/PERL) skills for physical design related issues is a must. Deep understanding of physical design flow and methodology is preferred.  

Minimum Requirements:

-  2+ yrs. of working experience in physical design with ICC2/FC tool set from netlist to GDS.

- Experience in low power physical design is a must.

- Scripting knowledge ( TCL/PERL)  for PD flow automation is a must.

- Debugging capability for PD flows is a must.

- Debugging capability for PV and STA flows is preferred.

- UPF knowledge is preferred.

- Experience in closure of high frequency and high congestion block level physical design is preferred.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

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Pay range and Other Compensation & Benefits:

$107,400.00 - $161,200.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.