Description:

Summary:

The purpose of this team is: The team are group of verification engineers. They test out designs before it becomes silicon. They are looking for someone to do pre-silicon verification work. This type of verification can span simulation and emulation, is not done by the same team in most silicon companies. Even in our company it is not in every team. Only a few teams does testing of this kind, multiple platforms based testing, its very unique.

Top 3 Hard Skills Required + Additional

1. Minimum 7 years experience with UVM/System Verilog

2. Minimum 7 years experience with scripting language

3. Minimum 7 years experience with write and debug tests in UVM

•\tMust be able to implement a UVM/System verilog test bench from scratch, create agents, scoreboards, checks, assertions, cover-points.

•\tMust know at least one scripting language (a plus if it is python).

•\tMust be able to write and debug tests in UVM, using Verdi source code level debugger.

•\tBachelors in Computer Science, Electrical/Electronics + 7 years verification experience using

•\tUVM/SystemVerilog Methodology OR Masters in Computer Science

•\tElectrical/Electronics + 5 years verification experience using UVM/SystemVerilog Methodology

Skills:

UVM, Verilog/System Verilog, scripting

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500.

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