Seeking a FPGA Manager with 8 to 10 years of experience. Reporting to the Director of Systems Engineering you will provide innovative solutions to our FPGA design effort.  This is a unique opportunity to create first to market chip designs and to contribute to the future of ATE instruments within COHU Semiconductor Test Group products. 

The job requires experience as a FW Engineering Manager responsible for leading a team for design and development equipment used in the semiconductor test industry. Also, the candidate must be very hands-on and not only have experience of FW architecture but also the selection and development of FPGA’s.

The job also requires coaching engineers and reviewing the design of engineers before design get released for prototyping.

Job function involves interaction with other functional groups and coordination with outside design resources.

Must be a self-motivated individual to work in a fast-paced high energy environment. This person must have project management skills including creating budget, resources assignment, schedules, as well as people management.

 

Essential Duties and Responsibilities:

This role provides detailed technical engineering in concert with the experienced staff of the ASIC and FPGA group.  This includes the implementation of the FPGA devices which provide support for the functions of different test instruments and in many cases the major portion of a test instrument’s capabilities. These features include:

Pattern generation with opcode driven vector generation for digital pin channels which drive signals to the device under test. DSP functionality in digitizers for analog waveform capture and analysis.  DIMM Memory access and pattern sequencing for AWG and DIG functions.  Power supply and analog channel instruments utilize FPGAs for PMU, switch and relay control, calibration DACs, sequencing, and ADC measurements.  All instruments also feature support for PCIe connectivity to access their functions.

Work activities include:

Manage a team of senior level FW engineers Project and People Management using Agile methodologies IC design using state-of-the-art AMD and Intel FPGA devices, including synthesis, place and route, timing constraints and closure. RTL module design, simulation test bench design and verification. IC characterization and lab bring-up. Designs are mainly targeted to FPGA devices but may also involve some ASIC work. Generation of technical documentation and reports. Working with the software and board design engineers to ensure proper integration of the IC into a complete test instrument.

 

Qualifications:

BSEE, BCE, MSEE, or PHD Minimum 8 years of work experience designing complex digital RTL modules and FPGAs is required.  Module RTL design, test bench development and module verification work experience is required AMD (Vivado) and/or Intel (Quartus Prime) tools work experience such as synthesis, place and route, static timing is required Proficiency using FPGA simulation tools such as Cadence Xcelium is required Verilog and System Verilog language work experience is required. Working knowledge of Python and C++ is desired.  English language proficiency is required Ability to use computer applications, including data analysis tools, word processing, spreadsheet, and presentation software.  Ability to work independently or as part of a team and follow through on assignments with minimal supervision.  Ability to complete assignments with attention to detail and high degree of accuracy.