Job Description
Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues.
Qualifications

Bachelor Degree in Electrical and Electronics Engineering or Master's Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience.

Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si.

Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al.

Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware.

Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation.

Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis.

Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers.

Knowledge in RTL design, VHDL/Verilog is a plus.

Strong analytical ability, problem solving and communication skills.

Ability to work independently and at various levels of abstraction.

Inside this Business Group
The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


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Working Model
This role will require an on-site presence.* Job posting details (such as work model, location or time type) are subject to change.