Company:Qualcomm Technologies, Inc.

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As part of the Qualcomm DTCO team in one of the largest fabless design powerhouses, the selected candidate will evaluate the most advanced logic technology from a DTCO and a PPA standpoint, with the ultimate goal of co-defining / optimizing technology features & entitlements with foundry and research partners. The selected candidate will be part of core-DTCO team responsible for pathfinding and validation of standard-cell (and block-level) DTCO boosters, for better Power and Performance, in technologies with advanced transistors architecture such as GAA / FINFET and advanced stdcell MOL schemes.

The ideal candidate would possess the following qualifications

Experience working with customers (internal & external), and cross-functional teams.Addon exposure/experience on 3DIC design implementation and STCO boosters explorations from RTL to full design PD Experience is a big plus.Experience working closely with foundry/EDA/research partners.Ability to work across diverse technical groups.Experience working in semiconductor R&D environments.

In addition to the above qualifications, the ideal candidate would also possess expertise in one or both of the following areas:

Block level DTCO/PPA

The selected candidate will be contributing to core-DTCO team for block-level synthesis to Physical Design (PD) based PPA activity/regression for DTCO boosters impact analysis at block level.The selected candidate will also be required to analyze and interpret the result of complex Power Performance Area (PPA) projects for DTCO and block level boosters.Finally, the selected candidate will actively participate in meetings with both internal cross functional teams and external Foundry/EDA/Research partners.

AND/OR

Technology Enablement and Floorplan, Power Grid and Power Switch Planning

Working closely with CAD team to enable new technology nodes  Floorplan guidelines development for new technology nodesPower grid specificationPower switch planningSupporting production teams in customizing power grid and switch planning per design requirementsProgramming skills using Python, Perl and tclFamiliarity with EDA tools specially Cadence Innovus

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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Pay range and Other Compensation & Benefits:

$98,500.00 - $147,700.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.