Minimum qualifications: + Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. + 2 years of experience in Automatic Test Pattern Generation (ATPG) methods. + Experience with multiple projects in Design for Testing (DFT) scan design and verification. + Experience with Design for Testing (DFT) techniques and tools, Application-Specific Integrated Circuit (ASIC) Design for Testing synthesis, simulation, and verification flow. Preferred qualifications: + Master's degree in Electrical Engineering. + Experience working with Automated Test Equipment (ATE) engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues). + Experience in System on a chip (SoC) cycles, including silicon bringup and silicon debug activities. + Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)). + Experience in fault modeling. Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will play a crucial role in Design for Testing (DFT), and support devices to production. You will be responsible for developing flows, automation, and methodology, executing DFT activities. You will be responsible for testing vectors end to end, from generating DFT content, debugging to coverage goals, simulating it at gate level, sign-off DFT to tapeout, and debugging results. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. + Execute activities in the design, implementation, and verification of Design for Testing (DFT) solutions for Application-Specific Integrated Circuit (ASICs). + Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG). + Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements. + Perform scan verification at Register-Transfer Level (RTL) and gate level. + Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.