Role Proficiency:

Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision

Outcomes:

     Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc.      Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time On time quality delivery approved by the project lead/manager

Measures of Outcomes:

     Quality –verified using relevant metrics by Lead/Manager      Timely delivery - verified using relevant metrics by Lead/Manager      Reduction in cycle time and cost using innovative approaches      Number of trainings attended      Number of new projects handled

Outputs Expected:

Quality of the deliverables:

Ensure clean delivery of the design and module in-terms of ease in integration at the top level Meet functional spec / design guidelines 100% of the time without any deviation or limitation Documentation of the tasks and work performed

Timely delivery:

Meeting project timelines as requested by the program manager Support the team lead in intermediate tasks delivery

Team Work:

Participation in team work; supporting team members/lead at the time of need Able to perform additional tasks in-case any team member(s) is not available

Innovation & Creativity:

Automate repeated tasks to save design cycle time as a necessary approach Participation in technical discussion
training
forum

Skill Examples:

     Languages and Programming skills:a.     System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one)      EDA Tools: a.     Cadence Synopsys Mentor tool sets (one or more)b.     Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one)      Technical Knowledge: (any one)a.     Partially implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb.     Strong in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec.      Strong knowledge in Physical Design / Circuit Design / Analog Layout d.     Strong understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione.     Strong knowledge of Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design      Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below      Strong communication skills      Good analytical reasoning and problem-solving skills with attention to details      Able to deliver the tasks on-time per quality guidelines and GANTT in every instance.      Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present to a level needed to execute the project

Knowledge Examples:

     Frontend / Backend / Analog Design:a.     Project experience in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b.     Strong understanding of the design flow and methodologies used in designing      Understanding of the technical specs and assigned tasks: Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill

Additional Comments:

Qualification/ Requirements : • 3 to 8 years of experience in SRAM Memories layout design.· • Should be well familiar with various levels of memory layouts from custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, decoders.· • Should have expertise in floor planning, power planning, block area estimation of memory designs or compliers.· • Should be able to perform leaf cell layout development and physical verification.· • Should have adequate knowledge of schematics, interface with circuit designer and CAD and process development team.· • Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.· • Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,· • Excellent in problem-solving skills in solving area, power, performance, and physical verification of custom layout.· • Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.· • Should have leadership qualities and able to do multi-tasking as required.· • Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.· • Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.· • Knowledge of Skill coding and layout automation is a plus. Role and Responsibilities· • Responsible for Memory Compiler layout development and verification.· • Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier, pre-charge, Control blocks for SRAM.· • Perform layout verification like LVS/ DRC/ Latchup, quality check and documentation.· • Responsible for on-time delivery of block-level layouts with acceptable quality.· • Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment.· • Guide junior team-members in their execution of Sub block-level layouts & review their work.· • Contribute to effective project-management.· • Effectively communicate with engineering teams in the India & Korea teams to assure the success of the layout project.