ASIC Design Engineer

Location: Bangalore

Experience: 7+ years

Opportunity Snapshot:

We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills. You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies. Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards.

Responsibilities:

Define and architect high-performance blocks for the latest, most advanced networking ASICs Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power Collaborate with the verification team in the development of the testplan and assist in debugging test failures Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

Required Skills:

7+ years of ASIC design experience Strong Verilog RTL coding skills Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus Knowledge of high performance memory subsystems Knowledge of multi-domain clock synchronization and high-speed serial interfaces Strong problem solving and ASIC debugging skills Excellent written and verbal communications skills MSEE or BSEE is required

 

 

Senior/Lead ASIC DV Engineer

IND, KA, Bangalore 

Juniper is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. We believe in excellence and we strive to achieve that through employee motivation, training and teamwork within a collaborative and innovative culture. 

Want to be apart of a fast paced team responsible for delivering high-speed ASICs for large, complex systems? Our team at Silicon Systems Technology Group (SST) is seeking ASIC Verification Engineers to verify next generation of ASICs for new core routers, switches, and firewalls. We are looking to hire sharp individuals with excellent communication, problem solving, and leadership skills. 

Opportunity Snapshot: 

At Juniper, you will have a significant opportunity to interact with system design teams across geographies. We are a team built on a foundation of open communications, empowerment, innovation, teamwork and customer success with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards. 

Responsibilities: 

You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.  Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. (30%)  Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity. (25%)  Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation. (30%)  Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%)  Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology (5%) 

Required Skills: 

ASIC Verification using SystemVerilog  Experience in constrained-random verification is a strong plus  Experience with verification methodology like OVM/VMM/UVM  Perl/Tcl scripting is strongly preferred  Experience verifying networking protocols such as Ethernet is desirable  Strong problem solving and ASIC debugging skills  MSEE or BSEE is required with at least 8 years of ASIC Verification Experience. 

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