**Summary:** Meta is hiring ASIC Front-End Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer, Front-End Implementation (University Grad) Responsibilities: 1. Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. 2. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. 3. Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities. 4. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures. 5. Perform RTL Lint and work with the Designers to create waivers. 6. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks. 8. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). 9. Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. **Minimum Qualifications:** Minimum Qualifications: 10. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. 11. Experience as a Front End Synthesis & Integration Engineer 12. Experience with RTL Synthesis and design optimization for Power, Performance, Area. 13. Knowledge of front-end and back-end ASIC tools. 14. Experience with RTL design using SystemVerilog or other HDL. 15. Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues. 16. Experience with communicating across functional internal teams and vendors. **Preferred Qualifications:** Preferred Qualifications: 17. Experience in SOC Design Integration and Front-End Implementation. 18. Knowledge of Physical Design flow such as Floorplanning, CTS, Routing 19. Knowledge of Timing/physical libraries, SRAM Memories. 20. Knowledge of STA signoff and understanding of AOCV, POCV 21. Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows 22. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools. **Industry:** Internet