At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known.

To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way.

About Juniper Networks

At Juniper, we strive to deliver network experiences that transform how people connect, work and live. By challenging the inherent complexity in the 5G and cloud era, our solutions power the connections that matter most - from education to healthcare to secure banking. Our commitment is to advance real outcomes for network teams and every individual they serve.

 

What You Will Do

Deliver physical design implementation of complex high performance networking silicon  Lead all aspects of physical design including chip area estimation, Chiplet partitioning, floor-planning, power estimation, synthesis, DFT, place and route, timing closure and sign-off. Build tools and improve existing infrastructure to optimize chip area and speed of execution. Interact with Design team to review constraints and achieve timing closure.  

 

Your Responsibilities Will Include

Collaborate with Cross Functional Teams (RTL, NPI, hardware design and test, component engineering and procurement) across geographies. Drive Physical Design Implementation in Advanced Process Nodes   Manage a team of physical design, DFT, circuit design and methodology development engineers Develop chip execution schedule and milestone tracking.  Communicate Status and Risks to Senior Management. Own power, performance and area optimization of design. Develop and drive processes and automation to ensure highest efficiency and quality
 

 

 Minimum Qualifications 

Demonstrable management experience in leading a team that does Physical Design.  Drive ASIC physical design methodology and flow from concept to release.  Previous demonstrated experience at leading and managing large ASIC developments in advanced process nodes. 

 

Preferred Qualifications 

Knowledge of industry standard PnR and signoff tools and their capabilities.  Understands the big picture and attention to detail during execution.  Prior Experience in developing Physical Design execution Schedule.  Knowledge and hands on experience in block level synthesis, place and route, timing closure.  Understanding advanced power analysis and power integrity analysis.  Knowledge of scripting languages Tcl, Python.  Manage Static Timing Analysis, timing closure and design constraints.  Self-motivated, able to work in a highly cross functional team.  MS or Bachelor’s in Electrical Engineering or Computer Science. 


 

 

Minimum Salary: $207,200.00

Maximum Salary:$297,850.00

The pay range for this position is expected to be between $207,200.00 and $297,850.00/year; however, the base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. The total compensation package for this position also includes medical benefits, 401(k) eligibility, vacation, sick time, and parental leave. Additional details of participation in these benefit plans will be provided if an employee receives an offer of employment.

If hired, employee will be in an “at-will position” and the Company reserves the right to modify base salary (as well as any other payment or compensation program) at any time, including for reasons related to individual performance, Company or individual department/team performance, and market factors.

Juniper’s pay range data is provided in accordance with local state pay transparency regulations. Juniper may post different minimum wage ranges for permanent residency petitions pursuant to US Department of Labor requirements.