Come join our fast paced, highly innovative Memory IO organization at Intel. Memory IO organization develops cutting edge Memory PHY IP for Intel’s SOCs.
Job Description:
Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed signal IPs.
Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models.
Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results.
Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals.
Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues.
influence partner teams on design and architectural tradeoffs
Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences. This is an experienced position and will be compensated accordingly.
Minimum Qualifications:
Candidate must possess a BS in electrical or computer engineering OR a MS in electrical or computer engineering and 12+ years' experience
Hands on Experience with circuit design, layout, circuit reliability tools/methodologies (IE: Cadence, Synopsys, etc.)
Design Experience in multiple analog projects through execution cycle
Experience using industry standard analog design tools from EDA vendors
Preferred qualifications:
Ph.D in Electrical or computer engineering and 10 years experience
Experience with analog design on advanced process nodes (either Intel or external foundry preferred)
Experience with DDR IO analog design is a plus
Annual Salary Range for jobs which could be performed in the US $214,730.00-$303,140.00
*Salary range dependent on a number of factors including location and experienceWorking ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.